ERI Programs

3D Heterogeneous Integration

Three Dimensional Monolithic System-on-a-Chip (3DSoC)

The overall goal of the Three Dimensional Monolithic System-on-a-Chip (3DSoC) program is to develop 3D monolithic technology that will enable > 50X improvement in System-on-a-Chip (SoC) digital performance at power. 3DSoC aims to drive research in process, design tools, and new compute architectures for future designs while utilizing U.S. fabrication capabilities. Read more.

Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS)

To enhance overall system flexibility and reduce design time for next-generation products, the Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS) program seeks to establish a new paradigm in IP reuse. CHIPS envisions an ecosystem of discrete modular, reusable IP blocks that can be assembled into a system using existing and emerging integration technologies. Modularity and reusability of IP blocks will require electrical and physical interface standards to be widely adopted by the community supporting the CHIPS ecosystem. Therefore, the program will develop the design tools and integration standards required to demonstrate modular integrated circuit (IC) designs that leverage the best of DoD and commercial designs and technologies. Read more.


Description forthcoming. Read more.

Photonics in the Package for Extreme Scalability (PIPES)

The Photonics in the Package for Extreme Scalability (PIPES) program seeks to develop high-bandwidth optical signaling technologies for digital microelectronics. By intimately integrating photonic and electronic components at the chip-package level, PIPES will overcome the physics-limited bottleneck of electrical data transfer between computing components. The development of efficient, high bandwidth package-level photonic signaling is anticipated to impact a host of applications, including machine learning, large scale emulation, high performance computing, advanced sensors and wireless interfaces. PIPES will aid commercial advances through technology investment, aligning these commercial outcomes with national security impact. Read more.


Description forthcoming. Read more.

Specialized Functions

Digital RF Battlespace Emulator (DRBE)

The Digital RF Battlespace Emulator (DRBE) program seeks to create a new breed of High Performance Computing (HPC) – dubbed “Real Time HPC” (RT-HPC) – that will effectively balance computational throughput with extreme low latency. DRBE will demonstrate RT-HPC domain-specific computing architectures by creating the world’s first largescale, virtual radio frequency (RF) test range, enabling more frequent and effective testing of RF systems. The DRBE test range will become a key part of DoD’s infrastructure, ushering in an era of system development and test based on 24/7/365 data generation. Commercial applications of RT-HPC are also expected, particularly in the area of big-data exploitation. Read more.

Domain-specific System on Chip (DSSoC)

The overall goal of the Domain-specific System on Chip (DSSoC) program is to develop a heterogeneous SoC comprised of many cores that mix general-purpose processors, special-purpose processors, hardware accelerators, memory, and input/output (I/O). DSSoC seeks to enable the rapid development of multi-application systems through a single programmable device. Read more.

Hierarchical Identify Verify Exploit (HIVE)

The Hierarchical Identify Verify Exploit (HIVE) program seeks to build a graph analytics processor that can process streaming graphs 1000X faster and at much lower power than current processing technology. If successful, the program will enable graph analytics techniques powerful enough to solve tough challenges in cyber security, infrastructure monitoring and other areas of national interest. Graph analytic processing that currently requires racks of servers could become practical in tactical situations to support front-line decision making. What’s more, these advanced graph analytics servers could have the power to analyze the billion- and trillion-edge graphs that will be generated by the Internet of Things, ever-expanding social networks, and future sensor networks. Read more.


Description forthcoming. Read more.

Near Zero Power RF and Sensor Operations (N-ZERO)

The Near Zero Power RF and Sensor Operations (N-ZERO) aims to develop the technological foundation for persistent, event-driven sensing capabilities. The resulting sensors could remain dormant, with near-zero power consumption, until awakened by an external trigger or stimulus. If successful, N-ZERO could extend the life of remotely deployed communications and environmental sensors—also known as unattended ground sensors (UGS)—from weeks or months to years, with implications for the Internet of Things. Read more.

Real-Time Learning Machines (RTML)

A critical challenge in computing is the creation of processors that can proactively interpret and learn from data in real-time, apply previous knowledge to solve unfamiliar problems, and operate with the energy efficiency of the human brain. Competing challenges of low-SWaP, low-latency, and adaptability require the development of novel algorithms and circuits specifically for real-time machine learning. To address real time embedded system challenges, the National Science Foundation (NSF) and DARPA have teamed up to explore rapid development of energy efficient hardware and ML architectures that can learn from a continuous stream of new data in real time. The goal of the DARPA RTML program is to create a compiler that can take ML frameworks, like TensorFlow and Pytorch, as an input and generate optimized Verilog code for hardware implementation. The RTML compiler is expected to enable rapid prototyping and design space exploration for next wave AI hardware. Read more.

Software Defined Hardware (SDH)

The goal of the Software Defined Hardware (SDH) program is to build runtime-reconfigurable hardware and software that enables near application-specific integrated circuit (ASIC) performance without sacrificing programmability for data-intensive algorithms. SDH aims to create a hardware/software system that allows data-intensive algorithms to run at near ASIC efficiency without the cost, development time, or single application limitations associated with ASIC development. Read more.

New Materials & Devices

Foundations Required for Novel Compute (FRANC)

The goal of the Foundations Required for Novel Compute (FRANC) program is to define the foundations required for assessing and establishing the proof of principle for beyond von Neumann compute architectures. FRANC will seek to demonstrate prototypes that quantify the benefits of such new computing architectures. Read more.

Technologies For Mixed-Mode Ultra Scaled Integrated Circuits (T-MUSIC)

The Technologies for Mixed-Mode Ultra Scaled Integrated Circuits (T-MUSIC) program seeks to disrupt RF mixed-mode technologies. T-MUSIC will develop integrated, ultra-broadband, mixed-mode electronics with embedded advanced digital CMOS electronics in a U.S. domestic foundry fabrication platform. The resulting highly integrated digital processing with intelligence on a chip will provide differentiated capabilities for DoD systems. It will enable next generation RF mixed-mode interfaces with an unprecedented combination of wide spectral coverage, high resolution, large dynamic range, and high information processing bandwidth. T-MUSIC will provide the foundation for enduring U.S. leadership in mixed-mode electronics technology for DoD and commercial 5G/6G wireless applications. Read more.

Design & Security


Description forthcoming Read more.

Circuit Realization at Faster Timescales (CRAFT)

The Circuit Realization at Faster Timescales (CRAFT) program seeks to shorten the design cycle for custom integrated circuits to months rather than years; devise design frameworks that can be readily recast when next-generation fabrication plants come on line; and create a repository of innovations so that methods, documentation, and intellectual property can be repurposed, rather than reinvented, with each design and fabrication cycle. This novel design paradigm could help diversify the innovation ecosystem by making it practical for small design teams to take on complex custom circuit development challenges that are out of their reach today. Reducing the time and cost for designing and procuring custom, high-efficiency integrated circuits, should drive the technology community toward best commercial fabrication and design practices and enable a versatile development environment where designers make decisions based on the best technical solutions without worrying about circuit design delays or costs. Read more.

Guaranteed Architectures for Physical Security (GAPS)

Today’s system owners have few guarantees about where their private, proprietary, or security sensitive data resides or of its secure movement between systems. The Guaranteed Architectures for Physical Security (GAPS) program will develop hardware and software architectures that provably guarantee the security of high-risk transactions, where data moves between systems of different security levels. GAPS will develop hardware and software co-design tools that allow data separation requirements to be defined during system design as well as protections that can be physically enforced at system runtime. These verifiable security properties may help create safer commercial systems useful for preserving proprietary information and protecting consumer privacy. Read more.

Intelligent Design of Electronic Assets (IDEA)

The overall goal of the Intelligent Design of Electronic Assets (IDEA) program is to create a “no human in the loop” layout generator that enables users with no electronic design expertise to complete the physical design of electronic hardware within 24 hours. IDEA plans to develop the algorithms, methodologies, and software required to create an automated, unified layout generator for mixed-signal integrated circuits, systems-in-package, and printed circuit boards. Read more.

POSH Open Source Hardware (POSH)

The overall goal of the Posh Open Source Hardware (POSH) program is to create an open source SoC design and verification ecosystem that will enable the cost effective design of ultra-complex SoCs. POSH seeks to create the hardware assurance technology required for signoff-quality validation of open source mixed signal SoCs, develop critical open source IP components, and demonstrate a high-performance open source SoC using the POSH ecosystem. Read more.

Performant Automation of Parallel Program Assembly (PAPPA, μE)

Description forthcoming. Read more.

Safeguards against Hidden Effects and Anomalous Trojans in Hardware (SHEATH, μE)

Description forthcoming. Read more.

System Security Integrated Through Hardware and Firmware (SSITH)

The System Security Integrated Through Hardware and Firmware (SSITH) program seeks to secure DoD and commercial electronic systems against software-enabled threats by developing novel hardware/firmware security architectures and hardware design methodologies. The program will investigate flexible hardware architectures that adapt to and limit the impact of new cybersecurity attacks while maintaining the performance and power required for system operation. Read more.


Electronics Resurgence Initiative: Defense Applications (ERI:DA)

To explore emerging and future applications of ERI technologies in defense contexts, the ERI: Defense Applications (ERI:DA) Broad Agency Announcement (BAA) will drive the development, demonstration, and application of ERI technologies for defense-specific systems. While national security is a consideration in all ERI programs, ERI:DA is a dedicated effort to ensure that promising technologies resulting from ERI investments reach defense-specific systems. The BAA will provide new opportunities to participate in ERI programs and increase connections between ERI efforts. Potential areas of exploration could include ERI applications in large-scale physical emulation, cognitive RF systems, next-generation satellites, cybersecurity, and beyond. Read more.

Joint University Microelectronics Program (JUMP)

Description forthcoming. Read more.

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