Increasing information processing density and efficiency
Data Protection in Virtual Environments (DPRIVE)
The Data Protection in Virtual Environments (DPRIVE) program seeks to enable FHE computation within a factor of ten of unencrypted computations, enabling data security for all states of data across DoD and commercial applications.
Foundations Required for Novel Compute (FRANC)
The goal of the Foundations Required for Novel Compute (FRANC) program is to define the foundations required for assessing and establishing the proof of principle for beyond von Neumann compute architectures. FRANC will seek to demonstrate prototypes that quantify the benefits of such new computing architectures.
Hierarchical Identify Verify Exploit (HIVE)
The Hierarchical Identify Verify Exploit (HIVE) program seeks to build a graph analytics processor that can process streaming graphs 1000X faster and at much lower power than current processing technology. If successful, the program will enable graph analytics techniques powerful enough to solve tough challenges in cyber security, infrastructure monitoring and other areas of national interest. Graph analytic processing that currently requires racks of servers could become practical in tactical situations to support front-line decision making. What’s more, these advanced graph analytics servers could have the power to analyze the billion- and trillion-edge graphs that will be generated by the Internet of Things, ever-expanding social networks, and future sensor networks.
Software Defined Hardware (SDH)
The goal of the Software Defined Hardware (SDH) program is to build runtime-reconfigurable hardware and software that enables near application-specific integrated circuit (ASIC) performance without sacrificing programmability for data-intensive algorithms. SDH aims to create a hardware/software system that allows data-intensive algorithms to run at near ASIC efficiency without the cost, development time, or single application limitations associated with ASIC development.
Structured Array Hardware for Automatically Realized Applications (SAHARA)
The Structured Array Hardware for Automatically Realized Applications (SAHARA) program aims to expand access to domestic manufacturing capabilities to tackle challenges hampering the secure development of custom chips for defense systems.
Hyper-Dimensional Data Enabled Neural Networks (HyDDENN) (AIE)
The Hyper-Dimensional Data Enabled Neural Networks (HyDDENN) topic in the Artificial Intelligence Exploration program seeks new data enabled neural network (NN) architectures to break the reliance on large MAC-based DNNs. HyDDENN will explore and develop innovative data representations with shallow NN architectures based on efficient, non-MAC, digital compute primitives to enable highly accurate and energy efficient AI for DoD edge systems.
Photonic Edge AI Compact Hardware (PEACH) (AIE)
The Photonic Edge AI Compact Hardware (PEACH) topic in the Artificial Intelligence Exploration program seeks novel AI processing architectures in combination with innovative photonic hardware that can leverage the inherent speed and inherent multi-dimensional processing diversity of photonic signals to enable breakthrough AI functionalities with significant reductions in hardware complexity.
Signal Processing in Neural Networks(SPiNN) (AIE)
The Signal Processing in Neural Networks (SPiNN) topic in the Artificial Intelligence Exploration program will develop a new set of advanced neural network (NN) computing kernels, which embed established physics-based mathematical digital signal processing (DSP) models.
Performant Automation of Parallel Program Assembly (PAPPA) (μE)
The Performant Automation of Parallel Program Assembly (PAPPA) topic in the Microelectronics Exploration program will explore tradeoffs between programming productivity, solution generality, and scalability to enable scientists and domain experts with no understanding of parallel programming and hardware architectures to create highly efficient performance portable programs.
Accelerating innovation in AI hardware to make decisions at the edge faster
Lifelong Learning Machines (L2M)
The Lifelong Learning Machines (L2M) program seeks to achieve paradigm-changing developments in AI architectures and ML techniques. The program seeks to develop systems that can learn continuously during execution and become increasingly expert while performing tasks, are subject to safety limits, and apply previous skills and knowledge to new situations - without forgetting previous learning.
Overcoming the inherent throughput limits of 2D electronics
Three Dimensional Monolithic System-on-a-Chip (3DSoC)
The overall goal of the Three Dimensional Monolithic System-on-a-Chip (3DSoC) program is to develop 3D monolithic technology that will enable > 50X improvement in System-on-a-Chip (SoC) digital performance at power. 3DSoC aims to drive research in process, design tools, and new compute architectures for future designs while utilizing U.S. fabrication capabilities.
Lasers for Universal Microscale Optical Systems (LUMOS)
The Lasers for Universal Microscale Optical Systems (LUMOS) program aims to bring high performance lasers and amplifiers to manufacturable photonics platforms through heterogeneous integration of diverse materials. LUMOS seeks to develop integrated photonics technology along three vectors: scaling complexity, scaling power, and scaling spectrum. To achieve improved scaling in complexity, LUMOS seeks to integrate thousands of lasers and amplifiers with highly complex photonic integrated circuits for applications such as compact optical phased array LiDAR and neuromorphic optical computing. To achieve power scaling, LUMOS will aim to develop Watt-class lasers on a low-loss, high-speed photonics platform for radio frequency (RF) and microwave applications. For scaling across the spectrum, LUMOS aims to create photonic circuits with integrated lasers operating across the visible spectrum with a wavelength-by-design methodology to enable atomic microsystems for positioning, navigation, and timing applications, as well as compact quantum sensors and information processing systems.
Photonics in the Package for Extreme Scalability (PIPES)
The Photonics in the Package for Extreme Scalability (PIPES) program seeks to develop high-bandwidth optical signaling technologies for digital microelectronics. By intimately integrating photonic and electronic components at the chip-package level, PIPES will overcome the physics-limited bottleneck of electrical data transfer between computing components. The development of efficient, high bandwidth package-level photonic signaling is anticipated to impact a host of applications, including machine learning, large scale emulation, high performance computing, advanced sensors and wireless interfaces. PIPES will aid commercial advances through technology investment, aligning these commercial outcomes with national security impact.
Technologies For Mixed-Mode Ultra Scaled Integrated Circuits (T-MUSIC)
The Technologies for Mixed-Mode Ultra Scaled Integrated Circuits (T-MUSIC) program seeks to disrupt RF mixed-mode technologies. T-MUSIC will develop integrated, ultra-broadband, mixed-mode electronics with embedded advanced digital CMOS electronics in a U.S. domestic foundry fabrication platform. The resulting highly integrated digital processing with intelligence on a chip will provide differentiated capabilities for DoD systems. It will enable next generation RF mixed-mode interfaces with an unprecedented combination of wide spectral coverage, high resolution, large dynamic range, and high information processing bandwidth. T-MUSIC will provide the foundation for enduring U.S. leadership in mixed-mode electronics technology for DoD and commercial 5G/6G wireless applications.
Mitigating the skyrocketing costs of electronic design
Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS)
To enhance overall system flexibility and reduce design time for next-generation products, the Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS) program seeks to establish a new paradigm in IP reuse. CHIPS envisions an ecosystem of discrete modular, reusable IP blocks that can be assembled into a system using existing and emerging integration technologies. Modularity and reusability of IP blocks will require electrical and physical interface standards to be widely adopted by the community supporting the CHIPS ecosystem. Therefore, the program will develop the design tools and integration standards required to demonstrate modular integrated circuit (IC) designs that leverage the best of DoD and commercial designs and technologies.
Intelligent Design of Electronic Assets (IDEA)
The overall goal of the Intelligent Design of Electronic Assets (IDEA) program is to create a “no human in the loop” layout generator that enables users with no electronic design expertise to complete the physical design of electronic hardware within 24 hours. IDEA plans to develop the algorithms, methodologies, and software required to create an automated, unified layout generator for mixed-signal integrated circuits, systems-in-package, and printed circuit boards.
Posh Open Source Hardware (POSH)
The overall goal of the Posh Open Source Hardware (POSH) program is to create an open source SoC design and verification ecosystem that will enable the cost effective design of ultra-complex SoCs. POSH seeks to create the hardware assurance technology required for signoff-quality validation of open source mixed signal SoCs, develop critical open source IP components, and demonstrate a high-performance open source SoC using the POSH ecosystem.
Real-Time Machine Learning (RTML)
A critical challenge in computing is the creation of processors that can proactively interpret and learn from data in real-time, apply previous knowledge to solve unfamiliar problems, and operate with the energy efficiency of the human brain. Competing challenges of low-SWaP, low-latency, and adaptability require the development of novel algorithms and circuits specifically for real-time machine learning. To address real time embedded system challenges, the National Science Foundation (NSF) and DARPA have teamed up to explore rapid development of energy efficient hardware and ML architectures that can learn from a continuous stream of new data in real time. The goal of the DARPA RTML program is to create a compiler that can take ML frameworks, like TensorFlow and Pytorch, as an input and generate optimized Verilog code for hardware implementation. The RTML compiler is expected to enable rapid prototyping and design space exploration for next wave AI hardware.
Intelligent Auto-Generation and Composition of Surrogate Models (DITTO) (AIE)
The Intelligent Auto-Generation and Composition of Surrogate Models (DITTO) topic in Artificial Intelligence Exploration program will explore novel third-wave AI solutions to this problem through the lens of microelectronic system simulation. If successful, the Ditto program will result in a comprehensive, automated software framework that can take in a microelectronic system design, train effective ML surrogate models of sub-system components (which incorporate some knowledge about the real-world component they represent), and can integrate these ML models in a way that allows them to expand/collapse into appropriate levels of hierarchy while maintaining acceptable levels of accuracy and coverage.
Overcoming security threats across the entire hardware lifecycle
Safeguards against Hidden Effects and Anomalous Trojans in Hardware (SHEATH)(μE)
The goal of the Safeguards against Hidden Effects and Anomalous Trojans in Hardware (SHEATH) Microsystems Exploration topic is to identify and demonstrate technical feasibility for real-time detection against hardware Trojans installed in complex COTS circuit boards. Technologies which detect anomalous excursions with low probability of false alarms could involve any of the following: single-stream or multi-modal sensing, side-channel extractions, trigger discovery via active stimulation, or performance-based machine learning architectures.
Automatic Implementation of Secure Silicon (AISS)
The Automatic Implementation of Secure Silicon (AISS) program aims to ease the burden of developing secure chips. AISS seeks to create a novel, automated chip design flow that will allow security mechanisms to scale consistently with the goals of a chip design. The target design flow will provide a means of rapidly evaluating architectural alternatives that best address the required design and security metrics, as well as varying cost models to optimize the economics versus security trade-off. The target system on chip (SoC) will be automatically generated, integrated, and optimized, and will consist of two partitions – an application specific processor partition and a security partition implementing the on-chip security features. By bringing greater automation to the chip design process, the burden of security inclusion can be profoundly decreased.
Guaranteed Architectures for Physical Security (GAPS)
Today’s system owners have few guarantees about where their private, proprietary, or security sensitive data resides or of its secure movement between systems. The Guaranteed Architectures for Physical Security (GAPS) program will develop hardware and software architectures that provably guarantee the security of high-risk transactions, where data moves between systems of different security levels. GAPS will develop hardware and software co-design tools that allow data separation requirements to be defined during system design as well as protections that can be physically enforced at system runtime. These verifiable security properties may help create safer commercial systems useful for preserving proprietary information and protecting consumer privacy.
System Security Integrated Through Hardware and Firmware (SSITH)
The System Security Integrated Through Hardware and Firmware (SSITH) program seeks to secure DoD and commercial electronic systems against software-enabled threats by developing novel hardware/firmware security architectures and hardware design methodologies. The program will investigate flexible hardware architectures that adapt to and limit the impact of new cybersecurity attacks while maintaining the performance and power required for system operation.
Revolutionizing communications (5G and beyond)
Digital RF Battlespace Emulator (DRBE)
The Digital RF Battlespace Emulator (DRBE) program seeks to create a new breed of High Performance Computing (HPC) – dubbed “Real Time HPC” (RT-HPC) – that will effectively balance computational throughput with extreme low latency. DRBE will demonstrate RT-HPC domain-specific computing architectures by creating the world’s first largescale, virtual radio frequency (RF) test range, enabling more frequent and effective testing of RF systems. The DRBE test range will become a key part of DoD’s infrastructure, ushering in an era of system development and test based on 24/7/365 data generation. Commercial applications of RT-HPC are also expected, particularly in the area of big-data exploitation.
Domain-specific System on Chip (DSSoC)
The overall goal of the Domain-specific System on Chip (DSSoC) program is to develop a heterogeneous SoC comprised of many cores that mix general-purpose processors, special-purpose processors, hardware accelerators, memory, and input/output (I/O). DSSoC seeks to enable the rapid development of multi-application systems through a single programmable device.
Millimeter-wave Digital Arrays (MIDAS)
The goal of the Millimeter-Wave Digital Arrays (MIDAS) program is to create the digital array technology that will enable next-generation DoD millimeter wave systems. The program seeks to develop element-level digital beamforming that will support emerging multi-beam communications and directional sensing of the electromagnetic environment in the 18-50 GHz band.
Joint University Microelectronics Program (JUMP)
DARPA, along with companies from the semiconductor and defense industries—Intel, IBM, Micron, Analog Devices, EMD Performance Materials, ARM, Samsung, TSMC, Raytheon, Northrop Grumman, and Lockheed Martin—have initiated the Joint University Microelectronics Program (JUMP) with six research centers to undertake high-risk, high-payoff research that addresses existing and emerging challenges in microelectronic technologies. JUMP comes at an inflection point in the history of the semiconductor industry where application and system research is critical to enabling the development of superior electronic systems to meet both DoD and commercial needs.
Circuit Realization at Faster Timescales (CRAFT)
The Circuit Realization at Faster Timescales (CRAFT) program seeks to shorten the design cycle for custom integrated circuits to months rather than years; devise design frameworks that can be readily recast when next-generation fabrication plants come on line; and create a repository of innovations so that methods, documentation, and intellectual property can be repurposed, rather than reinvented, with each design and fabrication cycle. This novel design paradigm could help diversify the innovation ecosystem by making it practical for small design teams to take on complex custom circuit development challenges that are out of their reach today. Reducing the time and cost for designing and procuring custom, high-efficiency integrated circuits, should drive the technology community toward best commercial fabrication and design practices and enable a versatile development environment where designers make decisions based on the best technical solutions without worrying about circuit design delays or costs.
Near Zero Power RF and Sensor Operations (N-ZERO)
The Near Zero Power RF and Sensor Operations (N-ZERO) aims to develop the technological foundation for persistent, event-driven sensing capabilities. The resulting sensors could remain dormant, with near-zero power consumption, until awakened by an external trigger or stimulus. If successful, N-ZERO could extend the life of remotely deployed communications and environmental sensors—also known as unattended ground sensors (UGS)—from weeks or months to years, with implications for the Internet of Things.