Dr. Pooya Tadayon

Dr. Pooya Tadayon

Fellow and Director of Assembly and Test Pathfinding / Intel Corporation

Dr. Pooya Tadayon

Pooya Tadayon is an Intel Fellow and Director of Assembly & Test Pathfinding within Intel's Technology Development group. His responsibilities include defining Intel's packaging and test roadmap, and delivering the building blocks required to enable the roadmap. His current focus is on advanced packaging technologies to enable 2.5/3D ICs and assembly/test solutions for co-packaged photonics that can scale to high volume. Prior to his current role, he was Director of Test Pathfinding from 2011-2018 and Director of Test Technology Integration from 2006-2011. He currently holds 30 patents, with more than three dozen pending, spanning the fields of test interconnect technology, thermal technology, and package/product architecture. Pooya received a B.S. degree in chemistry from the University of Washington in 1993 and a Ph.D. degree in physical chemistry from Oregon State University in 1998.

Presentation Date/Time:
Tuesday, August 22, 2023

3D IC EDA: What is Needed, and How/When Can We Deliver?
(1:50pm - 2:05pm)

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